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circuit note cn - 0269 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0269 . devices connec ted /referenced ad7984 18- bit, 1.33 msps pulsar 10.5 mw adc in msop/qfn ad8475 precision, selectable gain , fully differential funnel amp ad8065 high performance, 145 mhz fastfet op amps ADG5208 high voltage, latch - up proof, 8- channel multiplexers adg5236 high voltage latch - up proof, dual spdt switches adr44 4 ultralow noise, 4.096 v, ldo xfet voltage references with current sink and source 18 - bit, 1.33 msps, 16 - channel data acquisition system rev. 0 circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely respons ible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cau se whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3 113 ? 2013 analog devices, inc. all rights reserved. evaluation and desig n support circuit evaluation boards cn - 0269 circuit evaluation board (eval - cn02 69 - sdpz) system demonstration platform (eval - sdp - cb1z) design and integration files schematics, layout files, bill of materia ls circuit function and benefits the circuit shown in figure 1 is a high performance industrial signal level multichannel data acquisition circuit tha t has been optimized for fast channel - to - channel switching. it can process 16- channel s of single- ended inputs or 8 - channel s of differential inputs with up to 18 - bit resolution. a single channel can be sampled at up to 1.33 msps with 18 - bit resolution. a channel - to - channel switching rate of 250 khz between all input channels provides 16 - bit performance. the signal processing circuit combined with a simple 4 - bit up - down binary counter provide s a simple and cost effective way to realize channel - to - channel sw itching without an fpga, cpld , or high speed process or. the counter can be programmed to count up or count down for sequentially sampling multiple channels , or can be loaded with a fixed binary word for sampling a single channel . figure 1. multi c hannel data a cquisition c ircuit (simplified s chematic: all components, c onnections , and d ecoupling not s hown ) ai0 ai1 ai2 ai3 ai4 ai5 ai6 ai7 ai8 ai9 ai10 ai 11 ai12 ai13 ai14 ai15 single ended 1k ? 10k ? 1.25k ? 1.25k ? 1.25k ? 1.25k ? ?in_0.8* +in_0.8* +out ?out +vs ?vs ?in_0.4* +in_0.4* vcom nc ad8475 10 ? 10 ? 0.1 f 0.1 f 50v 0.1 f 50v 0.1 f 50v tp_1 vin nc_1 gnd tp_2 nc_2 vout trim adr444 2.2nf in+ in? gnd ref sdi sck sdo cnv vdd vio ad7984 vdd nc_1 d1 nc_3 gnd nc_2 nc_4 vss s1 a s1b in1 in2 nc_5 s2b s2 a d2 adg5236 1k ? 1k ? 1k ? 1k ? ad8065 ad8065 2.2nf p4 0 ? 33 ? 33 ? 33 ? 33 ? 33 ? 33 ? 15 ? 33 ? 33 ? 33 ? 1 3 2 jp3 1 3 2 jp4 b a y p1 q3 p0 p3 q1 gnd pe vcc q0 ce p cp tc p2 q2 u/d cet 74 l vc169 ch0 ch1 ch2 ch3 s6 s5 gnd s8 a1 d a0 s4 s3 s2 s1 vdd a2 en s7 vss ADG5208 s_d vio tclkbf d at a tfs +2.5v +4.096v +5v +12v ?12v en +5v dgnd agnd vcom +3.3v p0 p1 p2 p3 pl u/d ai0+ +12v ?12v ai1+ ai2+ ai3+ ai4+ ai5+ ai6+ ai7+ ai0? ai1? ai2? ai3? ai4? ai5? ai6? ai7? s6 s5 gnd s8 a1 d a0 s4 s3 s2 s1 vdd a2 en s7 vss ADG5208 +12v ?12v differentia l sport gpio 74 l vc1g00 +12v ?12v +12v ?12v 22 f 6.3v 10563-001
cn-0269 circuit note rev. 0 | page 2 of 12 this circuit is an ideal solution for a multichannel data acquisition card for many industrial applications including process control, and power line monitoring . circuit description the circuit shown in figure 1 is a classic multichannel non - synchronous data acquisition signal chain consisting of a multiplexer, amplifier s , and a n adc. the architecture allows fast sampling of multiple channels using a single adc, providing low cost and excellent channel - to - channel matching. channel - to - channe l switching speed is limited by the settling time of the various components following the multiplexer in the signal chain , because the multiplexer can present a full - scale step voltage output to the downstream amplifier and adc. the components in this circ uit have been specifically chosen to minimize the settling time and maximize channel - to - channel switching speed. component selection the ADG5208 mul tiplexer switches one of eight inputs to a common output, as determined by the 3 - bit binary address lines. the adg5236 contains two independently sel ectable single- pole/double throw (spdt) switches. t wo ADG5208 switches , combined with one adg5236 , allow 16 single- ended channels or 8 true differential channels to be connected to the rest of the signal chain using a 4- bit digital control signal. the 4 - bit digital signal is generate d by a 4- bit binary up / down counter triggered by the same signal used for the convert (cnv ) input to the 18 - bit, 1.33 msps ad7984 adc. the ad8065 j fe t input op amp has a 145 mhz bandwidth and is configured as a unity - gain buffer to provide excellent settling time performance and extremely hi gh input impedance. the ad8065 also provides very low impedance output to drive the ad8475 funnel amp attenuation stage . the advantages of fully differential signal chain are good common - mode rejection and reduction in second - order distortion products . in order to process 10 v industrial level signal s by modern low voltage differential input adcs, the a ttenuation and level shifting stage is necessary. the ad8475 , fully differential, attenuating (funnel) amplifier with integrated precision gain resistors provides precision attenuation ( by 0.4 or 0.8 ), common - mode level shifting, and single - ended - to - differential conversion along with input overvoltage protection. fast s ettling time (50 ns to 0.001% ), and low noise performance (10 nv/hz) make the ad8475 well s uited to drive 18- bit differential input adc s at sampling rates up to 4 m sps . the ad7984 , 18 -b it, pulsar ? adc selected in this circuit provides 18- bit resolution at 1.33 msps when sampling a single channel . however, the settling time of various components in the signal chain limit the overall accuracy when sequentially switching between channels. for example, 16 - bit performance is achieved when switching between channels at a 250 khz rate. timing analysis when the circuit shown in figure 1 is operating in the continuous s witching mode, all the 16 - channel signal - ended or 8 - channel differential signal streams are merged into a time - division multiplexed signal by the two stage multiplexer comprised of the ADG5208 and the adg5236 . the multiplexed signal drives the buffer circuit ( ad8065 ) and the attenuation and level s hift circuit ( ad8475 ). the output signal of the ad8475 drives the differential input adc through an rc filter (2.2 nf, 10 ? ). the multiplexed input signal typically consists of large voltage steps when switching between channels. in the worst case, one channel is at negative full scale, while the next channel is at positive full scale. therefore , t he step can be as large as the full range of input signal, in this case, 20 v. it is a tremendous challenge for the analog signal chain to settle to high precision from such a large step signal level in a short time . t he timing of the circuit must be carefully examined to determine the amount of settling time available at various sampling rate s and t he settling time required by the circuits in the signal chain. figure 2 shows the basic timing diagram of the system, and this is where the analysis starts. figure 2. multi c hannel data a cquisition c ircuit t iming acquisition [0000] [0001] settling t o ch0 settling t o ch1 conversion t conv t acq acquisition t s t md t dd t settle cnv sta tus [ch3 t o ch0] v out _sw 10563-002
circuit note cn-0269 rev. 0 | page 3 of 12 digital delay in the circuit shown in figure 1 , the adc and m ultiplexer are both triggered by the rising edge of cnv signal from digital controller. at this point, the sar adc has complete d the acquisitio n of the sample and start s the conversion cycle . ideally, the signal chain has one full sampling period to settle to the next channel , b ut there are delays in the digital circuit s that decrease the available settling time. in figure 2 , t dd is the sum of the delay through the nand gate and the counter clk - to - out delay . this digital delay can be found from the data sheet of each component , and is approximately 8 ns total . the time shown as t md in figure 2 is the delay through t he t wo stage multiplexer measured from the 50% point of the digital input to the point that the analog output signal start s to settle . since the ADG5208 and adg5236 are switched simultaneously in this circuit, the t md marked in figure 2 is equal to the delay generated by the slower one, which is the ADG5208 . the transition time delay of multiplexer is e asy to find in the data sheet. however , the transition delay on the data sheet is the delay time between the 50% of the digital input and the 90% point of the digital output as shown in figure 3 . so t md is calculated using the equation : t md = t transition ? t settle (90%) (1) the maximum settling time left for analog signal chain at a sampling rate of ? ? can be estimated b y the equation : t settle(fs) = 1/ f s C t dd ? t md (2) a good first order approximation for estimating multiplexer settling time i s to treat the multiplexer in the on state as a simple rc circuit with time constant of r on c d . the time for switch to settl e to within a % error can be calculated by the equation below. see the an - 1024 application note, how to calculate the settling time and sampling rate of a multiplexer for more details. the test circuit for measuring the transition delay with a load of 300 ||35 pf is shown in figure 3 . under this test configuration, the settling time can be estimated by equation 3. ( ) ld l on l on settle cc rr rr error t + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 100 % ln ? (3) figure 3. ADG5208 trans i
cn-0269 circuit note rev. 0 | page 4 of 12 for the ADG5208 , r on is 160 , and c d is 52 p f. the transition delay of ADG5208 is 160 ns . so, the 90% settling time of the ADG5208 is ( )( ) ns21pf35pf52 160 100 10 ln ? %) 90( =+? ? ? ? ? ? ? ? ? = 300 || settle t from e quation 1 , t md = t transition C t settle(90%) = 160 ns C 21 ns = 139 ns therefore , under this circuit configuration with the ADG5208 and the adg5236 , the total extra time delay due to the digital circuit s is t dd + t md = 8 ns + 139 ns = 147 ns actually, this digital delay of 147 ns due to the digital control circuit and part of the transition delay from multiplexer can be compensated by delaying the rising edge of the convert signal with respect to the m ultiplexer update signal by an amount of time equal to t dd + t md . however, both t dd and t md are a function of temperature, power supply voltage, and normal variations from part to part. the time margin mu st be enough to account for the variation and drift. for example, under this configuration with 147 ns digital delay, switching the multiplexer 100 ns to 120 ns ahead of the adc convert signal (t ahead ) increases the available settling time by the same amount . the optimized timing is shown in figure 4 , but was not implemented in the actual circuit in order to minimize complexity. figure 4. optimized t iming of m ulti c hannel data a cquisition c ircuit m ctr l 0000 0001 t o ch0 settling t o ch1 conversion t conv t ahead t ac acisition t s t md t dd t settle cnv sta ts ch3:ch0 votsw 10563-004
circuit note cn-0269 rev. 0 | page 5 of 12 settling time analysis when the circuit shown in figure 1 is operating in the continuous switching mode, all the 16 - channel signal - ended or 8- channel differential signal streams are merged into a time - division multiplexed signal by the two stage multiplexer , the ADG5208 and adg5236 . the signal is then buffered by the ad8065 that has a high impedance, low capacitance input . th en the low impedance output of ad8065 buffe r drive s the ad8475 stage that attenuates, level shifts, and performs the single- ended to differential conversion. an rc (10 ?, 2.2 nf) filter is place d at the input of the ad7984 adc in order to limit out - of - band noise and attenuate the kickback from the switched capacitor input of the adc . the ?3 db bandwidth of the filter is 7.2 mhz. (see front - end amplifier and rc filter design for a precision sar analog - to - digital converters , analog dialogue 46- 12, december 2012 ). for the purposes of calculating settling time, the circuit can be divided into four part s as shown in figure 5 . figure 5. sub -stage b lock d iagr am for s ettling t ime a nalysis then the total settling time is estimated to be the root sum squ a re (rss) of settling time of each stage 2 _ 2 _ 2 _ 2 _ _ rc s atn s buf s mux s all s ttttt +++ = in order to set tle to within a specific error band at a sampling rate , f s , the relationship below must be satisfied. t s_all + t dd + t md < 1/ f s or, f s <1/( t s_all + t dd + t md ) settling time for the multiplexer stage the equivalent circuit for a cmos switch can be approximated as an ideal switch in seri es with a resistor (r on ) and in parallel with two capacitors (c s , c d ). the multiplexer stage and associated filters can therefore be modeled as shown in figure 6 . figure 6 . first -o rder m odel for i nput p re -f ilter, m ultiplexer, and ad8065 i nput note that the adg5236 model does not show the series switch because it only switches when changing from single - ended to differential mode inputs. t he p re - filter in front of multiplexer is not shown in figure 1 . this pre - filter is used for noise suppression. also, the r p resistor combined with protection diodes and the tvs pro vides additional transient and over - voltage protection for hostile environment s. the protection components are shown in the complete circuit schematic contained in the cn - 0269 design support package . the r s is the 1 k? resistor in seri es with non - inverting input of the ad8065 , and c in is the input capacitance of ad8065 . the input impedance of ad8065 is 1 g ||2 .2 pf , and the 1 g resistance can be ignored . the circuit in figure 6 was simulated using ni multisim ? as shown in figure 7 , with the following component values: pre - filter: r p = 300 ; c p = 120 pf; ADG5208 : r on =160 ; c s = 5.5 pf; c d = 52 pf; adg5236 : r on =160 ; c s = 2.5 pf; c d = 12 p f; ad8065 : r s =1 k; c in = 2. 2 pf; figure 7. ni multisim s imulation c ircuit for the pre -f ilter, m ultiplexer , and ad8065 i nput p art 3 a ttenu a tion ad8475 p art 1 t s_mux t s_buf t s_ a tn mux ADG5208 adg5236 p art 4 rc + adc ad7984 t s_rc p art 2 buffer ad8065 10563-005 d c s c s c d v ss c s v ss v ss c d v ss v ss v ss v ss v ss sw1 sw2 r p r p ADG5208 adg5236 r on r on r on c p c p ai 1 ai 2 pre-filter r s c in ad8065 10563-006 sw1 sw2 r p 1 300 300 160 1k 160 160
circuit note cn-0269 rev. 0 | page 6 of 12 the simulation result is shown in figure 8 . from the simulation result, the settling of the circuit shown in figure 7 is: t s_mux = 10.1300 C 8.0011 = 2.129 s figure 8. pre -f ilter, m ultiplexer, and ad8065 i nput s ettling t ime s imulation because the multiplexer settling time is 2.1 s, this will l imit the maximum throughput rate per channel to 476 ksps (1/2.1 s), even if the multiplexer was the on ly element in the signal chain. since the settling time contributions of each stage in the signal chain add on an rss basis, stages having settling times of less than approximately 2.1 s 3 = 700 ns will have a minimum effect on the total settling time. settling time for ad8065 buffer and ad8475 attenuation stage s the settling time of an amplifier is defined as the time it takes the output to respond to a step change at the input and come into and remain within a defined error band, as measured relative to the 50% point of the input pulse, as shown in figure 9 . figure 9. settling t ime of an o p a mp the error band is usually defined to be a specific percentage of the step, such as 0.1%, 0.01%, 0.001%, etc. as shown in figure 9 , the dead time, slew time, and recove ry time together constitute the total settling time. for a high speed fast settling op amp, such as ad8065 , the dead time is only a small percentage o f the total settling time and can usually be ignored. op amp settling time is nonlinear; it may take 30 times as long to settle to 0.01% as to 0.1%. thermal effects within the op amp can cause the op amp to take hundreds of microseconds to settle to 0.01% , although 0.1% settling may be less than 100 ns. some op amps that have a settling time specified to 0.1% may never settle to 0.01% or 0.001% due to low amplitude ringing and/ or long term thermal effects . s ettling time is also a function of the op amp closed - loop gain and the feedback network, as well as the compensation. settling time depends on the amplitude of the output voltage step. a large output step generally has a longer settling time than a small one. m easuring 0.01% or 0.001% settling time for a 10 v or 20 v output ste p is an extremely difficult task due to the effects of oscilloscope overdrive, sensitivity, and the difficulty of generating an input pulse that settles to the required accuracy. the ad8065 op amp has a 0.1% settling time specification of 250 ns for a 10 v output step and a slew rate of 180 v/s. the slew time for the output to swing 10 v is approximately 55 ns, and the slew time for a 20 v output step is approximately 110 ns. we can estimate the 0.1 % settling time for a 20 v step by adding the additional slew time to the specification for a 10 v step, and obtain approximately 250 ns + 55 ns = 305 ns. based on empirical data, we will assume the 0.01% settling time is approximately 600 ns for a 20 v output step. the ad8475 differential attenuating amplifier has a settling time specification of 50 ns to 0.0001%, and a slew rate of 50 v/s for a 2 v output step. in the circuit, the output is 8 v, so assuming that the settling time is proportional to the output voltage step, the 8 v settling time will be approx imately 200 ns. settling time for the noise f ilter and the ad7984 adc t he ad7984 adc is a member of the pulsar ? family and is based on a charge - redistribution digital - to - analog converter c apacitive dac. the output code is determined in two phases. the first phase is the acquisition phase. the internal capacitive dac is switched to the adc input pins in order to acquire the signal. the external support circuitry driving the adc input must be able to settle to the required voltage at the end of acquisition phase. the adc then enters the conversion phase , and the capacitiv e dac is disconnected from the input . the conversion is then performed during this phase using the sar conversion algorithm . t he equivalent analog input circuit combined with the external rc filter is shown in figure 10 . the r ext and c ext are the external filter in fro nt of the adc , which is 10 ? and 2.2 nf in this circuit. the pin capacitance (c pin ) of several pf can be ignored because of the large c ext .the value of r in is typically 400 , and c in is typically 30 pf . figure 10 . ad7984 i nput e quivalent c ircuit ?2.9 7 8 9 10 time ( s) 11 12 13 1.5 volt age (v) 5.9 10.3 14.7 19.1 28.0 23.6 (8.00 11 ?10) (10.13 10) mux_ctr l output 2 1 10563-008 output error band fina l settling recove ry time slew time settling time dead time 10563-009 c pin ref r in c in d1 d2 in+ or in? gnd gnd gnd r ext c ext ad7984 10563-010
circuit note cn-0269 rev. 0 | page 7 of 12 during the conversion phase, the switch is open and the r ext and c ext time constant determines the input settling time. when the switch is closed and the adc enters the acquisition phase, the internal r in and c in is connected in parallel with the external network, and a charge transient can be injected onto the input. in this circuit, with a 0.4 gain of the ad8475 and a 20 v single-ended input step, the voltage step into the ad7984 is 4 v single-ended and 8 v differential. when the step voltage is initially applied, the ad8475 is in the conversion mode, and the switch is open. the r ext and c ext time constant is 22 ns, and 12.48 time constants is 275 ns (time required to settle to 18 bits shown in table 1), which is less than the 500 ns allowable conversion time when sampling at 1 msps. when the ad7984 enters the acquisition mode at the end of the 500 ns interval, the switch closes. at this point, the voltage at the rc filter input can be positive full-scale, and the voltage on c in can be negative full-scale, or vice-versa. the settling time of the voltage across c in is now a function of r ext , c ext , r in , and c in . the settling time for this circuit can be simulated by the multisim and is shown in figure 11. the sin is a component of multisim named pulse_voltage which provides the 4 v step input with 50% duty cycle. another pulse_voltage in figure 11 is sw_adc. this pulse_voltage combined with ideal switch a1 controls the conversion and acquisition cycle timing of the sar adc. the pulse is 500 ns wide which equals the conversion time of the ad7984 . the 5 s is the half- period of the input switching signal. the sin and sw_adc are controlled by the same phase of the clock. the switch a1 is open during the first 500 ns after sin is switched. switch a1 then closes, allowing the capacitive dac to acquire the input signal from the external rc filter. figure 11. multisim settling time model of the ad7984 front end the simulation result is shown in figure 12. the blue label shows that the voltage on c in settled to 4 v with 18-bit accuracy 469 ns after the input step signal. therefore the total settling time of the front end of the ad7984 is t src = 469 ns. figure 12. settling time waveforms for ad7984 front end simulation model table 1 is useful and shows the number of time constants required to settle to a given accuracy for a simple rc network. table 1. number of time constants required to settle to a given accuracy for an simple rc network resolution, no. of bits lsb (%fs) no. of time constants = ? in (%error/100) 6 1.563 4.16 8 0.391 5.55 10 0.0977 6.93 12 0.0244 8.32 14 0.0061 9.70 16 0.00153 11.09 18 0.00038 12.48 20 0.000095 13.86 22 0.000024 15.25 the total settling time of the entire circuit shown in figure 1 can now be estimated: 2 _ 2 _ 2 _ 2 _ _ rcs atns bufs muxs alls ttttt ??? ? ns2270 469200600 2129 2 2 2 2 ????? therefore for settling to 18 bits, the maximum switching rate of this circuit is: f s < 1/(2270 ns + 147 ns) = 414 khz noise analysis the noise of the ad8065 buffer stage the noise sources in the signal chain of this circuit are the thermal noise from resistors and the voltage and current noise from the ad8065 and the ad8475 . the on resistance of the two switches is small enough to ignore. a simplified noise analysis model for the ad8065 circuit is shown in figure 13. xsc1 abcd g t not u1 r in 400 ? c in 30pf 4.5v, 0.5v sw_adc 0v, 5v 500ns, 5s sin 0.5v, 4.5v 5s, 10s a1 r ext 10 ? c ext 2.2nf rc filter adcinput 10563-011 14 15 16 910 time (s) 11 12 13 2 1 sin sw_adc rc ext out (11.0469 4) 10563-012
cn-0269 circuit note rev. 0 | page 8 of 12 figure 13 . ad8065 n oise m odel the noise sources shown in figure 13 must be converted to the output by multiplying the noise gain, which is 1 for a unity - gain buffer. e ad8065_rto = 22 2 2 22 2 2 )( pf psp v rf rs rp irirreeee + +++++ the noise from resistors can be calculated from the equation: hznv/ 1000 4 r e r = at 25c where r is in ?. e rp = 2.2 nv/hz e rs = e rf = 4 nv/hz e v = 7 nv/hz i p = i n = 1 pa/hz e vad8065 = 10 nv/hz the noise of the ad8475 attenuation stage the e ad8065_rto term is the noise from the circuit at the input to ad8475 stage. this noise is reflected to the output of the ad8475 by multiplying the signal gain (0.4) of a d8475 stage as shown in figure 14 . figure 14 . ad8475 n oise m odel the ad8475 output voltage noise is also 10 nv/hz , i nclud ing amplifier voltage and current noise, as well as noise of internal resistors. the noise density of the whole signal chain in front of adc is ( ) 2 2 _ 2 ad8475_rto ad8475_rto ad8475 gain total e e gain e + = for the 10 v input range , the gain ad8475 = 0.4. e total _0.4 = 11.5 nv/hz for the 5 v in put range, the gain ad8475 = 0.8. e total_0 .8 = 15.1 nv/hz the total output noise of the ad8475 is applied to the rc filter (10 ?, 2.2 nf) that has a bandwidth of 7.23 mhz. the bandwidth of the ad8065 is 145 mhz, and the bandwidth of the ad8475 is 150 mhz. the input bandwidth of the ad7984 adc is 10 mhz, therefore the noise at the input of the ad7984 is limited by the rc noise filter to 7.23 mhz. when the ad8475 is operating at a gain of 0. 8 (worst case noise condition) the input rms noise to the adc is therefore v 51 mhz 23 .7 57 .1 hznv/ (15.1 _ = = rms total v v total_pp = 6.6 51 v = 337 v for the 18- bit ad7984 with reference voltage of 4.096 v, the differential input span is 8.196 v. the lsb value is 31 v. the peak - to - peak noise of 337 v therefore corresponds to 11 lsbs peak - to - peak. effect of multiplexer switching transient s t he multiplexer has source and drain capacitance . the drain capacitance of the multiplexer holds the voltage of previous input channel . when the mult iplexer switches to the next channel, this can create a transient or kick - back glitch through the r on resistance. this transient can affect the next conversion. therefore , the pre - filter driver needs to have a very low output impedance and a fast settling time to the transient. figure 15 . multiplexer s witching t ransients the driver need s to be able to charge the input to the required accuracy (forward - charge) before the switch opens . the back - charge occurs when the switch opens, and generally is short and doesnt present a problem. in order to make the circuit easy to drive , a buffer can be placed in front of the multiplexer (front buffer). the evaluation board e va l - cn0269 - sdpz has footprints for the input buffer on each input channel and has an ad8065 installed i n c hannel 1 to channel 4. adding the buffer slightly increase s the noise density and the settling time . however, in a practical application , the parasitic inductance and capacitance from the input cable or terminal connector will significantly increase the time of settling time and generate ringing du e to the forward and back charge without the buffer . the additional input buffer isolates the parasitic effects and provides very low impedance to the multiplexer. the d ifference in performance between the circuit with or without input buffer is shown in the test part of this circuit note. another reason for adding the input buffer is for that an additional filter can be placed ahead of it for anti - aliasing and noise reduction . ai r s r p ad8065 e rp e rs + ? r f e rf e v i p i n 10563-013 e ad8065_r to e ad8475_r to v n v p e ad8065_r to ad8475 + ? 10563-014 d c s c s c s c d c d v ss v ss v ss v ss sw1 sw2 r p v ss v ss v ss ADG5208 adg5236 r on r on r on c p c p r p ai 1 ai 2 pre-filter r s c in +10v ?10v p1 p2 p3 p1 p2 p3 sw_a0 kick back-charge fo rw ard-charge 10563-015
circuit note cn-0269 rev. 0 | page 9 of 12 histogram test results figure 16 shows the results of a 10,000 sample histogram taken by shortin g the 16 single - ended channels together and connect ing them to the gnd of the pcb. note that the peak - to - pea k noise is approximately 12 lsbs , including the input buffer. figure 16 . dc histogram at 0 v input, 1 msps s ampling rate, 10 , 000 samples ac test results the ac performance was tested at the system level with the ad7984 sampling at 300 ksps with 2.5 v p-p 10.675 khz input sine wave signal provided by a type 1051 b&k sine generator,. the circuit was sampling continuously on channel 4, and does not include the effects of the input buffer. the fft shows an snr = 91.33 dbfs. figure 17 . fft with a kaiser window (parameter = 20), 2.5 v p- p 10.675 khz i nput, 300 ksps s ampling rate on ch 4 without i nput b uffer switching speed and settling time test results the follow figures show the settling performance. the lab test setup is shown in figure 18 . figure 18 . switching s peed and s ettling t ime lab test s etup the cn - 0269 evaluation board was configured in the 16- channel singled input mode, the 8 odd channels were shorted together , and the 8 even channels were shorted together . a battery stack was used to generate the different dc input voltages for low noise and low impe dance. t he odd and even channels were connected to different voltage s. the lab view tm software controls the e va l - sdp - cb1z channel - to - channel and switches continually between the input channels. the switching rate was varied from 100 hz to 1 mhz in 1 khz increments. there were 10 samples taken at each switching rate, and the results averaged. the average value at the lowest switching rate was used as a reference point . the error at each different switching rate was cal cul ated by taking the difference between the 10 - sample and the reference value . the test result s are shown in figure 19 to figure 23. in the figures, an error of 2 lsbs corresponds to 17 - bit settling, and an error of 4 lsbs corresponds to 16 - bit settling. 10563-016 10563-017 shorting cable b & k type 1051 sine gener at or triple dc power supp ly agilent e3631 a ev al-sdp-cb1z ev al-cn0269-sdpz 1.5v b a tte ry s t ack 10563-018
cn-0269 circuit note rev. 0 | page 10 of 12 figure 19. errors vs. switching rate without front buffer at 16-channel single-ended, 14 v step figure 20. errors vs. switching ra te without input buffer, 8-channel differential mode, 14 v step figure 21. errors vs. switching rate with input buffer, 16-channel single-ended mode, 14 v step figure 22. errors vs. switching rate with front buffer, 8-channel differential mode, 14 v step figure 23. errors vs. switching rate with input buffer, 8-channel differential mode, 2 v step from the figures above, we can see the circuit with the input buffer has a better settling performance than the circuit without front buffer at switching rates less than 1 mhz. figure 21, figure 22, and figure 23 show that with the input buffer connected the circuit settles to 16 bits at channel-to- channel switching rates up to 250 khz. common variations the 18-bit ad7984 is available in a 10-lead msop or a 10-lead qfn (lfcsp) package. there are a number of other pulsar adcs available in the same package with 14-bit, 16-bit, and 18- bit resolutions having various sampling rates. another possible choice for the buffer amplifiers is the ad8021 . if programmable gain is required, the ad8250, ad8251 , and ad8253 have 685 ns settling time to 0.001%. the adg12xx series of multiplexers can be used if lower capacitance is required. 80 ?100 ?80 ?60 ?40 ?20 0 20 40 60 1000 0 100 200 300 400 500 600 700 800 900 error (lsb) switching rate (khz) ch 2, 4, 6? 16 settle to ?7v ch 1, 3, 5? 15 settle to +7v 10563-019 1000 0 100 200 300 400 500 600 700 800 900 30 ?40 ?30 ?20 ?10 0 10 20 error (lsb) switching rate (khz) ch 2, 4, 6, 8 settle to ?7v ch 1, 3, 5, 7 settle to +7v 10563-020 1000 0 100 200 300 400 500 600 700 800 900 error (lsb) switching rate (khz) 25 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 ch 2, 4, 6, ...16 settle to ?7v ch 1, 3, 5, ... 15 settle to +7v 10563-021 1000 0 100 200 300 400 500 600 700 800 900 error (lsb) switching rate (khz) 25 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 ch 2, 4, 6, 8 settle to ?7v ch1, 3, 5, 7 settle to +7v 10563-022 1000 0 100 200 300 400 500 600 700 800 900 6 ?6 ?4 ?2 0 2 4 error (lsb) switching rate (khz) ch 1, 3, 5, 7 settle to +1v ch 2, 4, 6, 8 settle to ?1v 10563-023
circuit note cn-0269 rev. 0 | page 11 of 12 circuit evaluation a nd test t his circuit uses the e va l - cn0269 - sdpz circuit board and the e va l - sdp - cb1z sdp - b system demonstration platform controller board . the two boards have 120 - pin mating connectors , allowing for the quick setup and evaluation of the performance of the circuit . the e va l - cn0269 - sdpz board contains the circuit to be evaluated, as described in this note, and the sdp -b controller board is used with the cn - 0269 evaluation software to capture the data from the e va l - cn0269 - sdpz circuit board . equipment needed the following equipment is needed: ? pc with a usb p ort and windows? xp (32 bit) , windows vista? , or windows 7 ? e va l - cn0269 - sdpz circuit b oard ? e va l - sdp - cb1z sdp - b c ontroller b oard ? cn - 0269 sdp evaluation software ? 6 v dc (500 ma), 12 v(300 ma) power supply ? low distortion signal generator to provide 10 v output with frequency from dc to 1m hz getting started load the e valuation s oftware by placing the cn - 0269 evaluation software in to the cd drive of the pc . using my computer , locate the drive that co nta ins the evaluation software . functional block diagram see figure 1 for the circuit block diagram and the e va l - cn0269 - sdpz - sch - revx .pdf file for the complete circuit schematic . this f ile is contained in the cn - 0269 design support package . a functional block diagram of the test setup is shown in figure 24. figure 24 . test s etup b lock d iagram setup connect the 120 - pin connector on the e va l - cn0269 - sdpz circuit board to the con a connector on the e va l - sdp - cb1z controller board (sdp - b) . use n ylon hardware to firmly secure the two boards, using the holes provided at the ends of the 120 - pin connectors . with power to the supply off, connect a 6 v and 12 v dc pow er supply to the pins on cn1, cn2 marked with +6 v , 12 v and gnd on the board . if available, a 6 v wall wart can be connected to the barrel connector on the b oard and used in place of the 6 v power supply . connect the usb cable supplied with the sdp -b board to the usb port on the pc . do no t connect the usb cable to the m ini - usb connector on the sdp -b board at this time . turn on the 6 v and 12 v power supply at the same time and then connect the usb cable to the mini - usb connector. test with the 6 v and 12 v power supply on, l aunch the e valu ation software . once usb communications are established, the sdp -b board can be used to send, receive, and capture data from the ev al - cn0269 - sdpz board and do the data analysis under time and frequency domain to evaluate the performance of the whole circuit . figure 25 shows a photo of the e va l - cn0269 - sdpz e valuation board connected . information regarding the sdp - b board can be found in the sdp - b user guide . information and details regarding test setup and calibration, and how to use the evaluation software for data capture ca n be found in the cn - 0269 software user guide . figure 25 . eval - cn0269 - sdpz evaluation board connectivity for prototype development the e va l - cn0269 - sdpz evaluation board is designed to be evaluated with th e e va l - sdp - cb1z sdp - b b oard based on the black - fin dsp through sport port ; however, any microprocessor can be used to inte rface to serial port of ad7984 through the 14 pin pmod connector . in order for another controller to be used with the e va l - cn0269 - sdpz evaluation board , software must be developed by a third party. there are existing interposer boards that can be used to interface to the altera and xilinx field programmable gate arrays ( fpgas ). the bemicro sdk b oard from altera can be used with the bemicro sdk/sdp interposer using nios drivers. any xilinx evaluation board that features the fmc connector can be used with the fmc - sdp interposer board. 6v dc 12v dc power supp ly ev al-cn0269-sdpz board cn1 and cn2 sdp connec t or pc ev al-sdp-cb1z sdp board 120 pins j2 ~ j5 jp3 usb usb cable jp4 10.000v + g ? signa l generat or 10563-024 10563-025
circuit note cn-0269 rev. 0 | page 12 of 12 learn more cn - 0269 design support package : http://www . analog . com/cn 0269 -designsupport ug - 277 user guide, sdp - b user guide , analog devices. alan, walsh. front - end amplifier and rc filter design for a precision sar analog - to - digital converter , analog dialogue 46- 12, december 2012. ard iz zoni, john. a practical guide to high - speed printed - circuit - board layout , analog dialogue 39 - 09, september 2005. kester, wa lt, data conversion handbook , chapter 8, section 8.2, multichannel data acquisition systems , elsevier. manning, michael. switch and multiplexer design considerations for hostile envir onments , ask the applications engineer - 40, analog dialogue, volume 45, may 2011. an - 359 application note, settling time of operational amplifiers, analog devices. an - 931, application note, understanding pulsar adc support circuitry , analog devices. an - 1024 application note , how to calculate the sett ling time and sampling rate of a multiplexer , analog devices. mt - 004 tutorial, the good, the bad, and the ugly aspects of adc input noise is no noise good noise? analog devices. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 035, op amp inputs, outputs, single - supply, and rail - to - rail issues , analog devices . mt - 046 tutorial, op amp settling time , analog devices. mt - 048 tutorial, op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth , analog devices. mt -0 74 tutorial, differential drivers for precision adcs , analog devices. mt - 088 tutorial, analog switches and multiplexers, analog devices. mt - 101 tutorial, decoupling techniques , analog devices. data sheets a nd evaluation boards cn - 0269 circuit evaluation board (eval - cn 0269 - sdpz) system demonstration platform (eval - sdp - cb1z) ad8065 data s heet ad8475 data s heet ADG5208 data s heet adg5236 data s heet ad 7984 data s heet adr444 data s heet revision history 11 /1 3 rev ision 0 : initial versio n (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of an alog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or otherwise under any patent s or other intellectual property by application or use of the circuits from the lab circuits. information furnished by analog devi ces is believed to be accurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do so. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10563 -0- 11/13(0)

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